重写过的项目源码在这里，实现的功能也写在 readme 里面了，这里不做过多赘述。简而言之，就是一个高度可扩展的物种演化模拟程序。

You can view the English translation of the post here, but it is only for reference.

痛点：模拟器层次的复杂度

由于项目要求限制¹，在交上去的代码里，模拟器层次有一个巨大的 switch 语句块，用来根据物种程序的指令类型来让底下的引擎执行不同的物理操作。下面是代码片段 (不完全是提交上去的代码，但是功能和结构一致)：

void Simulator::SimulateCreature(unsigned int creature_index) {
  ...
  current_instruction = engine_.get_instruction(creature_index);  // obtain current instruction
  ...
  switch (current_instruction.opcode) {
    case Opcode::kHop:  // hop forward
      engine_.MoveCreature(creature_index);
      break;
    case Opcode::kLeft:  // turn left
      engine_.TurnCreatureLeft(creature_index);
      break;
    ...
  }
  ...
}

功能上虽然没有问题，但是这种做法的缺点有不少：

• 单个函数体过于复杂；
• 如果将来要增加新的指令，需要再往这个 switch 里面增添东西，更加难以维护；
• 指令类型区分和指令执行全部耦合在一起，调试不方便。

事实上我本地的 code quality 工具直接警告这个 switch 语句块所在的函数复杂度过高，所幸评测机没卡这个点扣我分。

但为什么一开始会把指令执行放在模拟器里面呢？因为引擎归模拟器管理，而指令的执行又依赖于引擎提供的各种物理操作（例如前进、左转、感染前方生物等等）。

联想：嵌入式开发中学到的回调函数

在当初写完这个函数之后，我也一直在想能不能把指令执行从模拟器里面解耦出去。

某天洗澡的时候，我忽然回忆起嵌入式开发中学到的回调函数 (callback function)。回调函数一般是和中断 (interrupt) 搭配使用，用来在某个特定的事件发生时对其进行处理。老师教的基本架构是这样：

• 回调函数层：
  • 规定一个函数类型 (function type)，即函数的参数类型和个数以及函数的返回类型，不包括参数名称、函数名称和具体实现；
  • 开辟一个该类型函数的函数指针的数组作为注册表 (registry)；
  • 提供注册函数的接口以及执行所有已注册函数的接口。
• 应用层：
  • 实现具体的事件处理函数，要满足规定的函数类型；
  • 将处理函数的函数指针注册进回调函数层；
  • 在中断函数里直接调用回调函数层给的执行接口。

💡 在嵌入式领域，中断是实现事件处理的方式之一。当某个事件发生的时候，对应的设备会让单片机 (MCU) 知晓，这个时候单片机会中断正在执行的其他程序，转而处理这个刚刚发生的事件。

这种架构能让回调函数层完全不用知晓应用层要干什么，它只机械地执行应用层传过来的回调函数，因而在需求发生变更时也不用改动。这就是一种解耦的方式。

解决：依赖倒置

在上述的架构中，回调函数层不依赖于应用层的具体实现，而它俩都依赖于回调函数的函数类型。这就是依赖倒置原理 (Dependency Inversion Principle)。它要求：

高层次不应依赖于低层次；两者都应依赖于某个抽象 (abstraction)。

抽象不应依赖于实现细节；相反，实现细节应依赖于这个抽象。

在嵌入式的例子里，回调函数的函数类型就是这个抽象。而稍微迁移一下，依赖倒置原理也能应用在这个项目中。我是这样做的：

• 抽象出一个回调函数列表 WorldCallbacks，包含各种基本的物理操作（获取、设置、判断）；
• 抽象出一个执行方法的抽象类 IMethod，重载其括号运算符用于具体执行，接受上面的这个回调函数列表作为参数，同时让其为虚函数；
• 从执行方法的抽象类中继承出具体的各种动作 (action) 和感知 (sensor)，实现具体的执行过程。
• 在模拟器里维护一个 IMethod 类型的指针哈希表，指令名称作为其键值，方便快速调用。
• 让引擎提供 WorldCallbacks 的具体实现。

这个回调函数列表就是统一的抽象，模拟器层次和引擎层次都依赖于它。现在，在模拟器的执行逻辑里，只需要根据指令名称定位到对应的执行方法，然后调用其括号运算符，传入准备好的回调函数列表和其他相关参数即可。逻辑简单很多，如果要扩展的话也可以直接继承出一个新的执行类。

void Simulator::SimulateCreature(unsigned int creature_index) {
  ...
  current_instruction = engine_.get_instruction(creature_index);  // obtain current instruction
  ...
  std::shared_ptr<IMethod> executor = get_executor(current_instruction.opcode);  // obtain executor
  ...
  (*executor)(world_callbacks, creature_index, ...);  // dispatch the executor
  ...
}

重写过的这个 SimulateCreature 函数虽然看上去还会很复杂，但是其核心就是上面的这三行代码：获取指令、找到执行方法，传入参数执行。其它的都是一些检查判断之类的操作，是为了满足杂七杂八的其他需求。如果后续还要加新的功能的话，是完全不用动它的。

脚注

Here is the source code for the rewritten version. Since the functionality is also described in the readme, I won’t go into too much detail here. In short, it’s a highly extensible species evolution simulation program.

Note: This post is a translated version. See here for the original content.

Pain Point: Complexity in the Simulator Layer

Due to the project requirements¹, in the submitted code, the simulator layer had a huge switch statement block that directed the underlying engine to perform different physical operations based on the instruction type of the creature program. Below is a code snippet (not exactly the submitted code, but the functionality and structure are identical):

void Simulator::SimulateCreature(unsigned int creature_index) {
  ...
  current_instruction = engine_.get_instruction(creature_index);  // obtain current instruction
  ...
  switch (current_instruction.opcode) {
    case Opcode::kHop:  // hop forward
      engine_.MoveCreature(creature_index);
      break;
    case Opcode::kLeft:  // turn left
      engine_.TurnCreatureLeft(creature_index);
      break;
    ...
  }
  ...
}

Functionally, this works fine, but it has several drawbacks:

• The single function body is overly complex;
• Adding new instructions in the future would require modifying this switch block, making it harder to maintain;
• Instruction type discrimination and instruction execution are all coupled together, which makes debugging inconvenient.

In fact, my local code quality tool directly warned that the function containing this switch block had excessive complexity. Fortunately, the online judge didn’t give me a deduction for that.

But why was instruction execution placed inside the simulator in the first place? Because the engine is managed by the simulator, and the execution of instructions depends on various physical operations provided by the engine (e.g., moving forward, turning left, infecting the creature ahead, etc.).

Association: Callback Functions Learned in Embedded Development

After I finished writing that function, I kept thinking about whether I could decouple instruction execution from the simulator.

One day while showering, I suddenly recalled callback functions learnt from embedded development. Callbacks are typically used with interrupts to handle specific events when they occur. The basic architecture taught by the teacher was:

• Callback layer:
  • Define a function type (i.e., the parameter types, count, and return type of the function), excluding parameter names, function name, and concrete implementation;
  • Declare an array of function pointers of that type as a registry;
  • Provide an interface for registering functions and an interface for executing all registered functions.
• Application layer:
  • Implement the concrete event handlers, ensuring they conform to the specified function type;
  • Register the function pointers of these handlers into the callback layer;
  • Inside the interrupt service routine, simply call the execution interface provided by the callback layer.

💡 In embedded systems, interrupts are one way to handle events. When an event occurs, the corresponding device notifies the microcontroller (MCU), which then interrupts its current program to process the event.

This architecture allows the callback layer to be completely unaware of what the application layer does—it mechanically executes the callback functions passed to it. Thus, when requirements change, the callback layer does not need to be modified. This is a form of decoupling.

Solution: Dependency Inversion

In the architecture above, the callback layer does not depend on the concrete implementation of the application layer; instead, both depend on the function type of the callback. This is the Dependency Inversion Principle, which states:

High-level modules should not depend on low-level ones; both should depend on abstractions.

Abstractions should not depend on implementation details; implementation details should depend on abstractions.

In the example above, the function type of the callback is the abstraction. By extending this idea, the principle can also be applied to this project. Here’s what I did:

• Abstract a callback function list WorldCallbacks that includes various basic physical operations (getters, setters, checking methods);
• Abstract an execution method abstract class IMethod, override its function-call operator for concrete execution, taking the above callback list as a parameter, and make it virtual;
• Inherit from the execution method abstract class to create concrete actions and sensors, implementing their specific execution logic;
• In the simulator, maintain a hash table of IMethod pointers, keyed by instruction name for quick lookup;
• Have the engine provide the concrete implementation of WorldCallbacks.

This callback list serves as the unified abstraction, and both the simulator layer and the engine layer depend on it. Now, in the simulator’s execution logic, we only need to locate the corresponding execution method by the instruction name, call its function-call operator, and pass in the prepared callback list and other relevant parameters. The logic becomes much simpler, and for extensions, we can simply inherit a new execution class.

void Simulator::SimulateCreature(unsigned int creature_index) {
  ...
  current_instruction = engine_.get_instruction(creature_index);  // obtain current instruction
  ...
  std::shared_ptr<IMethod> executor = get_executor(current_instruction.opcode);  // obtain executor
  ...
  (*executor)(world_callbacks, creature_index, ...);  // dispatch the executor
  ...
}

Although the rewritten SimulateCreature function may still look complex on the surface, its core is exactly the three lines above: fetch the instruction, find the executor, and execute with parameters. Everything else consists of checks and validations to satisfy various other requirements. If new features need to be added later, this function never needs to be touched.

Footnotes

最快速的信息交换是并行 (parallel)，通过很多根线将数据的所有比特位全部同时传输，相当于修建一条十几个车道的高速公路，很多辆车可以同时行驶。但在嵌入式设计的领域，能够调用的硬件资源往往十分有限，从一个设备拉出十几根线仅仅为了传输某个特定的数据是相当不现实的。这种情况下，串行 (series) 就显得尤为必要，通过仅仅两三根线将数据的比特位在时间维度上依次发送，相当于开辟一条乡间小路，汽车必须一辆辆地依次通过。

虽然串行传输的速度往往比并行传输慢了好几倍，但是它极大地减少了面积和端口数，更加的经济。而且现在的硬件一般都能以兆赫兹级别的频率处理数据，需要多花费的时间在大部分的实际使用中都不会有太大的影响。

常用的串口通信协议有以下三种：

• SPI：Series Peripheral Interface，串行外围设备接口；
• I2C：Inter-Integrated Circuit，直译为“集成电路之间”；
• UART：Universal Asynchronous Receiver/Transmitter，通用异步收发器。

本文将涵盖这三种通信协议的硬件构造、数据传输以及各自的特殊机制。

The English translation of this post is provided here, only for reference.

一些基本概念

在接触协议的具体细节前，先来看传输中涉及的几个基本概念。

• 主机 (master) 和从机 (slave)：发起通信的称为主机，其余的设备称为从机。绝大多数情况下，MCU 作为主机，外设作为从机。需要注意的是，从机也可以向主机发送数据；谁是主机、谁是从机是根据整个传输过程的发起来确定的。
• 时钟信号 (clock signal)：由于数据串行传输，如何控制传输的“时机”就显得尤为重要。一种方法是将一个周期性的信号作为“节拍器”，主机和从机再根据这个“节拍器”来确定何时发数据，何时读数据。这个周期性的信号就被称为时钟信号。需要时钟信号的机制是同步 (synchronous) 的，反之就是异步 (asynchronous) 的。
• 边沿敏感 (edge-sensitive) 和电平敏感 (level-sensitive)：所谓的“边沿”和“电平”以时钟信号为参照。
  • 边沿是指时钟信号从低电平变为高电平或者由高电平变为低电平的变化过程，而“边沿敏感”指的就是数据是在某个特定的边沿 (上升沿 rising-edge/下降沿 falling-edge) 处被读出的；
  • “电平敏感”指的则是数据是在时钟信号位于某个特定的电平 (高或低) 时被读出的。

边沿敏感 (上升沿) 和电平敏感 (高电平) 的信号示意。

💡 如果数据信号是边沿敏感的，需要保证其在时钟信号指定边沿前后的一小段时间内保持恒定，否则会形成建立/保持时间违例 (setup/hold time violation)，容易导致系统进入亚稳态 (metastable state) 并影响功能的正确性。这是由硬件产生的限制，无法根除，且是高频数字 IC 设计的难点。

SPI：完整且灵活的通信协议

硬件构造

SPI 通信协议支持一个主机与多个从机之间通信，需要四种类型的连线。

SPI 协议硬件构造示意。

SPI 协议的设计允许数据以极高的速率传输，例如 STM32G473RCT6 就支持最高 8.0 MBit/s 的速率 (每秒传输 800 万个比特位)。同时由于输入和输出线分离，SPI 协议可实现全双工 (full-duplex) 通信，即由主机向从机发送的数据和由从机向主机发送的数据能同时传输。

数据传输

开始与停止

SPI 的片选线 CS 是低电平有效的。因此，SPI 的数据传输由片选线 CS 被设为低电平开始，在片选线 CS 被设为高电平时结束。

传输过程

SPI 的数据信号是边沿敏感的。其时钟信号由时钟线 SCK 搭载，我们可以调整时钟极性 (clock polarity, CPOL) 和时钟相位 (clock phase, CPHA) 来满足不同的外设。

• 时钟极性 CPOL：时钟空闲 (idle) 时的电平，可取 0 或 1：
  • 0 代表时钟空闲时位于低电平，
  • 1 代表时钟空闲时位于高电平。
• 时钟相位 CPHA：数据从时钟信号开始的第几个边沿开始采样，可取 0 或 1：
  • 0 代表使用从时钟信号开始的那个边沿，
  • 1 代表使用从时钟信号开始的那个边沿的后一个边沿。

SPI 协议时钟极性、时钟相位示意。

在两根数据线 MOSI 和 MISO 上，数据都是最高位 (MSB) 先出，意味着数据的高位先传输，低位后传输。下图展示了一个 SPI 协议的传输示例。

SPI 协议传输示例：主机向从机发送数据，CPOL = 0，CPHA = 0。

具体实现

SPI 传输协议在 MCU 上的实现有软件和硬件两种。

• 软件 SPI 就是通过 MCU 上的通用输入输出 (GPIO) 端口来控制 SPI 协议的四种连线，再通过代码操作 GPIO 来传输数据。
• 硬件 SPI 就是借由 MCU 内置的 SPI 相关模块实现传输，代码层面只需要调用对应的库函数即可。例如，在 STM32G4 系列的 MCU 上配置好相应的引脚后，我们可以直接调用 HAL_SPI_Transmit 和 HAL_SPI_Receive 这两个函数来借由 MCU 上的 SPI 模块实现发送与接收数据。

软件 SPI 通常比硬件 SPI 的传输速率会低一些。

💡 从更广泛的视角来看，解决同一个问题，通常软件实现都会比硬件实现的执行效率低。软件实现是间接的：所有代码最终都要翻译成机器码扔到一个处理器去执行，而处理器为了普适性一般不会为了某个具体的问题作优化。硬件实现则是直接的：将需求一步到位落地实现到数字逻辑中，设计出为了解决这个问题的专用的数字电路，因此可以优化到极致。

有现实的示例可供参考。在量化交易领域，计算速度至关重要：一个延迟了几毫秒的卖出操作就可能造成几千甚至上万元的损失。除了把计算程序的性能凹到极致，从业人士甚至还开始使用 FPGA (现场可编程门阵列) 来进行相关计算，因为 FPGA 的执行速度更快。FPGA 是更直接的硬件实现，它的内部是一些基本的逻辑元件，可以通过编程把它们连接起来，从而形成某个特定功能的数字电路。

以下是软件 SPI 的实例，代码基于 STM32G4 系列 MCU。

// CPOL = 0, CPHA = 0
void spi_transmit(const GPIO_TypeDef* CS_port, const uint16_t CS_pin, uint8_t data) {
  HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK low, idle 
  HAL_GPIO_WritePin(CS_port, CS_pin, GPIO_PIN_RESET); // CS low, start transmission

  for (int i = 7; i >= 0; --i) { // MSB first
    HAL_GPIO_WritePin(MOSI_port, MOSI_pin, (data & (1 << i)) ? GPIO_PIN_SET : GPIO_PIN_RESET);
    HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_SET); // SCK high, rising edge
    HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK back to low
  }

  HAL_GPIO_WritePin(CS_port, CS_pin, GPIO_PIN_SET); // CS high, end transmission
  HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK low, back to idle 
}

I2C：一根数据线控制权的巧妙调度

我们可以发现，SPI 有一个缺点：连线的数量还是太多了，尤其是片选线，每个从机都需要有一根。有没有办法减少连线的数量呢？

有的兄弟，有的。请看 I2C。

硬件构造

I2C 通信协议支持多个主机和多个从机之间的通信。它只需要两根线。

由于没有片选线，I2C 要求系统里的每个从机都要有一个独一无二的地址 (address) 以方便主机区分。

I2C 协议硬件线路连接示意。

我们看到，I2C 协议的时钟线 SCL 和数据线 SDA 都连接了一个上拉电阻 (pull-up resistor)。而在每个设备内，两根线各自都通过一个 NMOS 三极管接地。这与 I2C 产生电平的机制有关：

• 某个设备想输出低电平时，就让其 NMOS 三极管导通，将对应的线接地；
• 某个设备想输出高电平时，就断开其 NMOS 三极管释放对应的线，上拉电阻会把它拉到高电平。

因此，当空闲时，两根线都会处于高电平。

I2C 协议产生电平的机制。

💡 NMOS 三极管是 MOSFET (金属氧化物半导体场效应晶体管) 中的一种。NMOS 有三个端口，图中右上、右下的端口分别是漏极 (drain) 和源极 (source)，左侧的端口是栅极 (gate)。在这个电路中，NMOS 可以看作是一个由栅极电平控制的开关：当栅极为低电平的时候，源极和漏极之间不导通，开关断开；当栅极为高电平的时候，源极和漏极之间导通，开关闭合。

这种连接还产生了一个线与门 (wired-AND) 的效应：当多个设备想要往同一根线上输出的时候，

• 只有这些设备都想要输出高电平的时候，这根线才会是高电平；
• 反之，只要有一个设备想输出低电平的时候，这根线就是低电平。

I2C 利用这一效应避免了短路 (VCC 直接接地)，还实现了很多巧妙的机制，我们一会儿会讲到。

然而，由于 I2C 的高电平不是硬连接到 VCC 而是靠上拉电阻实现，电源就需要通过上拉电阻给整条线路的寄生电容 (parasitic capacitance) 充电。而上拉电阻的阻值一般不会太小，所以这个 RC 电路的时间常数比较大，因而从低电平到高电平的转换就会较为缓慢。这限制了 I2C 的传输速率，使其无法达到 SPI 的水平 (例如 STM32G473RCT6 的 I2C 最高传输速率只有 400 kBit/s，即每秒传输 40 万个比特位)。

此外，由于只有一根数据线，虽然主机可以向从机发送数据，从机也可以向主机发送数据，但是这两者不能同时进行。因此，I2C 只能实现半双工 (half-duplex)。

数据传输

开始与停止

I2C 的开始和停止比较特殊：

• 开始条件 (START condition)：在 SCL 为高电平时，SDA 由高电平变为低电平；
• 停止条件 (STOP condition)：在 SCL 为高电平时，SDA 由低电平变为高电平。

除此之外，还存在一个重复开始条件 (repeated START condition)，是在主机希望发起一个新的通信请求，但是不想发送停止条件从而释放两根线的控制权时使用的。

传输过程

I2C 的数据信号是电平敏感的。除了开始和停止条件之外，数据线 SDA 上的所有电平都是在时钟线 SCL 位于高电平时读取的。因此，在每个 SCL 的高电平期间，SDA 的电平应保持稳定，否则会被认为是开始或停止条件，导致执行错误。

在数据线 SDA 上，数据都是最高位先出的，且一般以字节为单位。I2C 还引入了确认 (acknowledge, ACK) 和不确认 (not acknowledge, NACK) 机制来让发送者知晓数据的接收情况：在每个字节发送完毕后，发送者会暂时释放数据线 SDA 一个时钟周期，接收者在这个时钟周期内会控制 SDA 的电平：

• 高电平表示不确认 (NACK)，接收者无法或不愿再接收数据；
• 低电平表示确认 (ACK)，接收者完整收到并处理了数据，告知发送者可进行接下来的操作。

需要注意的是，发送者不一定是主机，接收者也不一定是从机。从机也可以向主机发送数据。

💡 ACK 与 NACK 的电平高低是有讲究的：在一切正常的时候，接收者需要对数据线 SDA 的电平进行主动的操作。如果接收者本身故障了完全没有反应，它就不会动 SDA 的电平；而 SDA 的电平空闲时是高，对应 NACK，发送者一看，就知晓自己发送的数据并没有被接收者接收到。

I2C 协议传输一个字节的过程示意 (接收者在最后发送 ACK)。

I2C 的数据传输往往还遵循固定的格式。不同从机可能对数据的格式有不同的要求，但是大多数都包含从机地址、从机内部的寄存器地址，还有要传输的数据本体。以下图片来源于 IS31FL3731 的手册，它是一个 LED 矩阵的驱动器，使用 I2C 与 MCU 之间进行通信。

IS31FL3731 规定的数据传输格式。图片取自 IS31FL3731 的手册。

特殊机制

当一个多主机的系统采用 I2C 协议进行通信的时候，如何有序、高效地调度线路的控制权，就成为了一个问题。这时，I2C 协议的“线与门”机制就可以发挥威力了。

时钟同步 (Clock Synchronization)

多个主机产生的时钟信号虽然可以设置为相同的频率，但是相位和占空比很难保证完全一致。如何确定一个稳定的时钟信号，保证数据线 SDA 在这个时钟信号为高电平时是恒定的呢？

我们想到，在所有主机各自产生的时钟信号均为高电平时，它们想要往数据线 SDA 上输出的数据都是恒定的，所以 SDA 的电平就一定是恒定的。因此，这个稳定的时钟信号就可以通过所有的时钟信号取与获得。这并不需要任何额外的器件，因为 SCL 天然具有线与门的特性！这就是时钟同步。

I2C 的时钟同步机制示意。

仲裁 (Arbitration)

时钟是同步了，但是多个主机会尝试在同一个时间点开始发送数据，产生控制权的争夺。I2C 通过仲裁来确定哪个主机获得最终的控制权。

仲裁的规则十分简单：我们没办法阻止主机在同一个时间点开始发送数据，那就让它们一边发送各自的数据一边盯着数据线 SDA 看，谁先往 SDA 上发送高电平但是看到低电平，谁输掉仲裁 (lose arbitration) 并退出。输掉仲裁的主机需要释放 SDA，等待观测到停止条件后才能重新尝试发送数据。这一仲裁机制是去中心化的，没有一个统一的上层单元指挥，全靠各个主机的“自觉”判定。

由于 SDA 的线与门特性，某个主机因输掉仲裁而退出时，不会对仍在场上发送数据的主机产生任何影响，因为它尝试发送的是高电平；而输掉仲裁前，它们发送的一定是相同的数据。因此仲裁的过程对于所有从机而言都是透明的，无法察觉。

I2C 的仲裁机制示意。

时钟拉伸 (Clock Stretching)

有时，从机处理主机发送来的数据需要一定时间。由于时钟信号的产生并不由从机控制，如果在处理完成前主机发送的新数据就到达了，或者从机忙于处理数据没能及时拉低数据线 SDA 来应答 ACK，很容易造成传输的混乱和效率低下。

但是从机也并非束手无策。从机可以通过主动拉低时钟线 SCL 来延伸某个时钟周期低电平的时间，从而完成数据的处理。由于 SCL 具有线与门的特性，只要从机将其拉低，即使主机产生的时钟信号想将其置高，它也仍然是低电平。主机在观测这种情况时，也需要相应地延长自己产生的时钟信号的低电平时间，直至从机完成数据处理释放 SCL。这就是时钟拉伸。

I2C 的时钟拉伸机制示意。

具体实现

I2C 协议在 MCU 上的实现也有两种，硬件 I2C 和软件 I2C。但是由于 I2C 的机制比较复杂，软件实现也会很繁琐且执行效率低下，因此绝大部分情境下 I2C 协议都是通过硬件来实现的。在 STM32G4 系列 MCU 上，配置好 I2C 模块对应的引脚之后，代码中可以直接调用 HAL_I2C_Master_Transmit 和 HAL_I2C_Master_Receive 函数来实现硬件 I2C 向从机传输和接受数据。

UART：去除时钟线，实现异步全双工

I2C 协议的线路数量虽然只有 2 根，但是它只有一根数据线 SDA，只能实现半双工，就像单线铁路：如果有两列不同方向的列车交汇，其中一列就需要停车等待另一列完全通过之后才能通过。有没有办法既保留 I2C 线路少的优势，同时又将其改造成“双线铁路”实现全双工呢？

我们自然而然地把目光投向 I2C 的另一根时钟线 SCL，它的存在意味着 I2C 协议是同步的。如果把它砍了换成另一根数据线，就能重新实现全双工，但传输变成了异步。这就是 UART。

硬件构造

UART 协议只支持两个设备之间的通信，且没有严格的主机从机之分，因为两台设备的构造完全一致。每个设备均有两个端口，

• RX 用来接收数据，
• TX 用来发送数据。

每台设备的 RX 端口都与另一台设备的 TX 端口相连。这就实现了全双工，两台设备之间可以同时互相传输数据。

UART 协议硬件线路连接示意。

💡 一般来说，UART 应用在电脑主机与 MCU 之间的通信。在这种情况下，电脑主机通常被称为上位机 (host computer)。

数据传输

开始与停止

RX/TX 在空闲时为高电平。当 RX/TX 由高电平变为低电平时，传输开始；当数据传输完毕后，RX/TX 由低电平变为高电平，传输停止。开始和停止的条件在发生后也占一个数据位的时间，称为起始位 (START bit) 和停止位 (STOP bit)。

传输过程

由于没有统一的时钟来指挥，两台设备必须提前约定好很多东西，其中就包括波特率 (baud rate)。波特率是指每秒传输的符号数，单位 baud。在 UART 的语境下，波特率就等于每秒传输的比特位的数量，因为一个比特就由信号中的一个符号携带。UART 协议常用的波特率有 9600、19200 和 115200。

虽然波特率设为一致了，但是接收方看到的仍然只是一个光秃秃的数据信号。如果它一个周期只对这个数据信号采样一次，很容易出现严重的错误，因为没有参照点。UART 协议解决这个问题的方法是起始位同步 (START bit synchronization) 和过采样 (oversampling)：接收方在观测到起始位之后才开始接收数据，同时需要以约定好的波特率的若干倍来对数据信号采样。这个倍数一般是 2 的幂，通常采用 8、16 或者 32。

以 16 倍过采样为例，每 16 个采样周期对应一个数据位。接收者的采样流程如下：

• 观测到 RX 由高变低，开始采样；
• 经过 8 个采样周期后，观察 RX 是否仍为低，若是，将其作为起始位的中心点；若不是，则之前观测到的 RX 由高变低是噪声毛刺，停止采样。
• 每隔 16 个采样周期对 RX 进行采样，作为一个新的数据位的中心点；
• 在接收数据完毕之后停止采样。

此外，两台设备还需规定起始位和停止位之间传输多少比特位，在整个通信过程中都需要保持一致。我们还可以选择在一个数据传输完毕后添加一个奇偶校验位 (parity bit)，表示传输的数据中应该有奇数个还是偶数个高电平，方便接收者检验。

UART 协议硬数据传输示意：16 倍过采样，3 个数据位，无校验位。

当然，就像对好的时钟经过一段时间后会不精确一样，两台设备各自的波特率也可能会有小幅的差异，引起误差累积。不过理论上这个误差的影响不是很大，因为

• 每次数据传输之前都有起始位同步，因而误差累积被限制在一次数据传输之内；
• 通过过采样并且选择合适的采样时间点，我们还保证每次采样都大致在数据信号的中心点，即使有小幅误差也很难读取到错误的电平。

实际应用中，UART 协议可以忍受两台设备之间的波特率误差在 4% 左右。

具体实现

UART 协议一般通过专门的硬件实现，代码中只需要调用对应的底层函数即可。

除提供的底层函数之外，还存在许多开源的 UART 库可供使用，能极大简便调试和开发。例如，SerialAccessor 就是一个通过 UART 实现上位机对 MCU 寄存器直接访问的串口调试框架。有时间的话，我也会详细解析一下这个框架的运行机制，包括 DMA 缓冲区等等。

总结

我们详细讲述了 SPI、I2C，以及 UART 串口通信协议的基本原理。在实际应用中，可根据它们的特点和实际需求灵活使用。

参考资料

• Understanding the SPI Bus (SBOA621) - Texas Instruments
• Understanding the I2C Bus (SLVA704) - Texas Instruments
• Basics of I2C: Advanced Topics (TIPL6104) - Texas Instruments
• UART Protocol Overview - Texas Instruments
• IS31FL3731: Audio Modulated Matrix LED Driver - Lumissil Microsystems
• Description of STM32G4 HAL and low-layer drivers (UM2570) - ST Microelectronics

The fastest form of information exchange is parallel, where all the bits of a piece of data are transmitted simultaneously over many wires—like building a multi-lane highway where many cars can travel at the same time. However, in embedded design, hardware resources are often very limited, and pulling a dozen wires from a device solely to transmit a specific type of data is highly impractical. In this case, serial communication becomes essential: it transmits the bits of the data one after another in the time domain over just two or three wires, like opening a narrow country lane where cars must pass one by one.

Although serial transmission is often several times slower than parallel, it greatly reduces the required area and number of pins, making it much more economical. Moreover, today’s hardware can usually process data at megahertz frequencies; the extra time needed rarely has a significant impact in most real-world scenarios.

The three most commonly used serial communication protocols are:

• SPI: Serial Peripheral Interface;
• I2C: Inter-Integrated Circuit;
• UART: Universal Asynchronous Receiver/Transmitter.

This article covers the hardware configuration, data transmission, and special mechanisms of these three protocols.

Note: This post is a translated version. See here for the original content.

Fundamental Concepts

Before diving into the details of the protocols, let’s look at a few fundamental concepts involved in transmission.

• Master and Slave: The device that initiates the communication is called the master; the other devices are called slaves. In most cases, the MCU acts as the master and the peripheral as the slave. Note that a slave can also send data to the master; who is the master and who is the slave is determined by which device initiates the entire transfer.
• Clock Signal: Since data is transmitted serially, controlling the “timing” of transmission becomes particularly important. One approach is to use a periodic signal as a metronome, with the master and slave then using this metronome to determine when to send data and when to read it. This periodic signal is called the clock signal. Protocols that require a clock signal are synchronous; those that do not are asynchronous.
• Edge-sensitive and Level-sensitive: The terms “edge” and “level” refer to the clock signal.
  • An edge is the transition process of the clock signal from low to high or from high to low. “Edge-sensitive” means data is read at a specific edge (rising edge or falling edge).
  • “Level-sensitive” means data is read while the clock signal is at a specific level (high or low).

Edge-sensitive (rising edge) and level-sensitive (high level) signal illustration.

💡 If a data signal is edge-sensitive, it must remain stable for a short period before and after the specified clock edge; otherwise, a setup/hold time violation may occur, easily driving the system into a metastable state and affecting functional correctness. This is a hardware limitation that cannot be eliminated and is a challenge in high-frequency digital IC design.

SPI: A Complete and Flexible Communication Protocol

Hardware Configuration

The SPI protocol supports communication between one master and multiple slaves and requires four types of connections.

SPI protocol hardware configuration.

The SPI design allows data to be transmitted at extremely high speeds; for example, the STM32G473RCT6 supports a rate of up to 8.0 MBit/s (8 million bits per second). Moreover, because the input and output wires are separate, SPI can achieve full-duplex communication—data sent from the master to the slave and from the slave to the master can be transmitted simultaneously.

Data Transmission

Start and Stop

The SPI chip select wire CS is active low. Therefore, data transmission begins when CS is set low and ends when CS is set high.

Transmission Process

SPI data signals are edge-sensitive. The clock signal is carried on the SCK wire, and we can adjust the clock polarity (CPOL) and clock phase (CPHA) to meet the requirements of different peripherals.

• Clock Polarity (CPOL): The idle state level of the clock. It can be 0 or 1:
  • 0 means the clock idles low,
  • 1 means the clock idles high.
• Clock Phase (CPHA): Which edge of the clock signal to use for sampling, counted from the start of the clock signal. It can be 0 or 1:
  • 0 means use the first edge after the clock signal starts,
  • 1 means use the second edge after the clock signal starts.

SPI clock polarity and clock phase illustration.

On both the MOSI and MISO data wires, data is sent most significant bit (MSB) first, meaning the higher bits are transmitted before the lower bits. The figure below shows an example of an SPI transmission.

SPI transmission example: master sends data to slave, CPOL = 0, CPHA = 0.

Implementation

SPI can be implemented on an MCU in two ways: software SPI and hardware SPI.

• Software SPI uses general-purpose input/output (GPIO) pins to control the four SPI wires, with the code toggling the GPIOs to transmit data.
• Hardware SPI leverages the MCU’s built-in SPI module. At the code level, you only need to call the corresponding library functions. For instance, on STM32G4 series MCUs, after configuring the relevant pins, you can directly call HAL_SPI_Transmit and HAL_SPI_Receive to send and receive data using the on-chip SPI peripheral.

Software SPI typically achieves a lower transfer rate than hardware SPI.

💡 From a broader perspective, a software implementation is generally less efficient than a hardware implementation for the same problem. Software is indirect: all code is ultimately translated into machine instructions and executed on a general-purpose processor, which is not optimized for any specific task. Hardware is direct: the requirement is realized directly in digital logic, creating a dedicated digital circuit designed to solve that particular problem, which can therefore be optimized to the extreme.

A real-world example can be seen in quantitative trading, where calculation speed is critical—a sell order delayed by just a few milliseconds can cause losses of thousands or even tens of thousands of dollars. Beyond squeezing every bit of performance out of software, practitioners have even begun using FPGAs (Field-Programmable Gate Arrays) for relevant computations because they execute faster. An FPGA is a more direct hardware implementation; its internal structure consists of basic logic elements that can be connected through programming to form a digital circuit for a specific function.

Below is an example of software SPI, based on STM32G4 series MCUs.

// CPOL = 0, CPHA = 0
void spi_transmit(const GPIO_TypeDef* CS_port, const uint16_t CS_pin, uint8_t data) {
  HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK low, idle 
  HAL_GPIO_WritePin(CS_port, CS_pin, GPIO_PIN_RESET);   // CS low, start transmission

  for (int i = 7; i >= 0; --i) { // MSB first
    HAL_GPIO_WritePin(MOSI_port, MOSI_pin, (data & (1 << i)) ? GPIO_PIN_SET : GPIO_PIN_RESET);
    HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_SET);   // SCK high, rising edge
    HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK back to low
  }

  HAL_GPIO_WritePin(CS_port, CS_pin, GPIO_PIN_SET);   // CS high, end transmission
  HAL_GPIO_WritePin(SCK_port, SCK_pin, GPIO_PIN_RESET); // SCK low, back to idle 
}

I2C: Clever Scheduling of a Single Data Wire

We can see that SPI has one drawback: the number of wires is still relatively high, especially the chip select wire, which requires one per slave. Is there a way to reduce the number of wires?

Thankfully, there is. Take a look at I2C.

Hardware Configuration

The I2C protocol supports communication between multiple masters and multiple slaves. It requires only two wires.

Since there is no chip select wire, I2C requires each slave in the system to have a unique address so the master can distinguish them.

I2C protocol hardware wiring.

Notice that both the SCL clock wire and SDA data wire in I2C are connected to a pull-up resistor. Inside each device, both wires are connected to ground through an NMOS transistor. This relates to the way I2C generates its logic levels:

• When a device wants to output a low level, it turns on its NMOS transistor, pulling the wire to ground.
• When a device wants to output a high level, it turns off its NMOS transistor, releasing the wire, and the pull-up resistor pulls it high.

Therefore, when idle, both wires are at a high level.

I2C level generation mechanism.

💡 An NMOS transistor is a type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It has three terminals: the top-right and bottom-right ports in the figure are the drain and source, and the left port is the gate. In this circuit, the NMOS can be thought of as a switch controlled by the gate voltage: when the gate is low, the drain and source are not conducting (switch open); when the gate is high, they conduct (switch closed).

This connection also creates a wired-AND effect: when multiple devices try to output on the same wire,

• only if all of them want to output a high level will the wire be high;
• conversely, if any device wants to output a low level, the wire becomes low.

I2C exploits this effect to avoid short circuits (VCC directly to ground) and to implement many clever mechanisms, which we will discuss shortly.

However, because the I2C high level is not hard-wired to VCC but is achieved through a pull-up resistor, the power supply must charge the entire wire’s parasitic capacitance through that resistor. The pull-up resistor’s value is generally not very small, so the time constant of this RC circuit is relatively large, making the low-to-high transition fairly slow. This limits the I2C transfer rate, preventing it from reaching SPI levels (e.g., the STM32G473RCT6’s I2C maximum speed is only 400 kBit/s, i.e., 400,000 bits per second).

Furthermore, because there is only one data wire, although a master can send data to a slave and a slave can send data to the master, both cannot happen at the same time. Therefore, I2C can only support half-duplex communication.

Data Transmission

Start and Stop

The I2C start and stop conditions are special:

• START condition: while SCL is high, SDA transitions from high to low.
• STOP condition: while SCL is high, SDA transitions from low to high.

Additionally, there is a repeated START condition, used when the master wants to initiate a new communication without releasing the bus by sending a STOP condition first.

Transmission Process

I2C data signals are level-sensitive. Except during the start and stop conditions, all data on the SDA wire is read while SCL is high. Therefore, during each SCL high period, the level on SDA must remain stable; otherwise it may be interpreted as a start or stop condition, causing errors.

On the SDA data wire, data is sent MSB first and generally in bytes. I2C also introduces an acknowledge (ACK) and not-acknowledge (NACK) mechanism to let the sender know the reception status: after each byte is transmitted, the sender temporarily releases the SDA wire for one clock cycle, and the receiver controls SDA during that cycle:

• A high level indicates NACK: the receiver cannot or does not want to receive more data.
• A low level indicates ACK: the receiver has fully received and processed the data, telling the sender it can proceed with the next operation.

Note that the sender is not necessarily the master, nor is the receiver necessarily the slave. A slave can also send data to the master.

💡 The high/low assignment for ACK and NACK is deliberate: under normal operation, the receiver must actively drive the SDA wire. If the receiver itself is faulty and completely unresponsive, it will not drive SDA, leaving it at its idle high level: which corresponds to NACK. Upon seeing this, the sender knows that its data was not received.

I2C byte transmission process (receiver sends ACK at the end).

I2C data transfers often follow a fixed format. Different slaves may have different requirements, but most include a slave address, an internal register address within the slave, and the actual data to be transferred. The image below is taken from the IS31FL3731 datasheet; it is an LED matrix driver that communicates with an MCU using I2C.

Data transmission format specified by the IS31FL3731. Image from the IS31FL3731 datasheet.

Special Mechanisms

When a multi-master system adopts the I2C protocol, how to orderly and efficiently schedule control of the bus becomes an issue. This is where the “wired-AND” property of I2C shows its power.

Clock Synchronization

Even if multiple masters configure their clock signals to the same frequency, the phase and duty cycle can hardly be perfectly aligned. How can a stable clock be established to ensure that SDA is constant when the clock is high?

We realize that when all the clock signals generated by the individual masters are high, the data they want to output on SDA is meant to be stable, so the level on SDA will definitely be stable. Therefore, the stable clock signal can be obtained by ANDing all the individual clock signals. This requires no extra hardware, because SCL naturally possesses the wired-AND property! This is clock synchronization.

I2C clock synchronization mechanism.

Arbitration

The clocks are synchronized, but multiple masters may still attempt to start transmitting at the same moment, resulting in contention for the bus. I2C resolves this through arbitration.

The rule of arbitration is simple: we cannot prevent masters from starting at the same time, so we simply let them proceed by send their respective data while monitoring the SDA wire. Whichever master first sends a high level on SDA but observes a low level loses arbitration and withdraws. The master that loses arbitration must release SDA and may only try to transmit again after observing a STOP condition. This arbitration mechanism is decentralized—no unified higher-level unit commands it; it relies entirely on the “self-awareness” of each master.

Thanks to the wired-AND property of SDA, when a master loses arbitration and withdraws, it has no impact on the master still transmitting, because the withdrawing master was attempting to send a high level. Before losing, they must have been sending identical data. Therefore, the arbitration process is entirely transparent to all slaves; they cannot detect it.

I2C arbitration mechanism.

Clock Stretching

Sometimes a slave needs some time to process data sent by the master. Since the slave does not control the clock, if new data from the master arrives before processing is complete, or if the slave is too busy to pull SDA low in time to acknowledge, the transmission can easily become chaotic and inefficient.

But the slave is not powerless. It can actively pull the SCL wire low to extend the low period of a clock cycle, thereby gaining enough time to finish processing. Because of the wired-AND property of SCL, as long as the slave holds it low, even if the master tries to drive it high, it will remain low. The master, upon observing this, must correspondingly extend the low period of its own generated clock signal until the slave finishes processing and releases SCL. This is clock stretching.

I2C clock stretching mechanism.

Implementation

I2C can also be implemented in both hardware and software on an MCU. However, because the I2C protocol is rather complex, a software implementation would be cumbersome and inefficient; therefore, in the vast majority of scenarios, hardware I2C is used. On STM32G4 series MCUs, after configuring the pins for the I2C module, you can directly call HAL_I2C_Master_Transmit and HAL_I2C_Master_Receive to transmit and receive data via the hardware I2C peripheral.

UART: Removing Clock Wire to Achieve Async Full-Duplex

Although I2C uses only two wires, it has only one data wire SDA and can only achieve half-duplex—like a single-track railway: when two trains traveling in opposite directions meet, one must stop and wait for the other to pass completely. Is there a way to retain the low wire count of I2C while transforming it into a “double-track railway” to achieve full-duplex?

Naturally, we turn our attention to I2C’s other wire, SCL. Its existence makes I2C synchronous. If we replace it with another data wire, we can regain full-duplex, but the transmission becomes asynchronous. This is UART.

Hardware Configuration

The UART protocol supports communication between only two devices and has no strict master/slave distinction, because both devices are constructed identically. Each device has two ports:

• RX for receiving data,
• TX for transmitting data.

Each device’s RX is connected to the other device’s TX. This achieves full-duplex communication, allowing both devices to exchange data simultaneously.

UART protocol hardware wiring.

💡 Generally, UART is used for communication between a PC and an MCU. In this context, the PC is often referred to as the host computer.

Data Transmission

Start and Stop

RX/TX are idle high. A transmission starts when the wire transitions from high to low; after the data is transmitted, the wire transitions back from low to high, stopping the transmission. The start and stop conditions each occupy the time of one data bit and are called the start bit (START bit) and stop bit (STOP bit).

Transmission Process

Since there is no common clock to orchestrate them, the two devices must agree on many things in advance, including the baud rate. Baud rate refers to the number of symbols transmitted per second, measured in the unit of baud. In the UART context, baud rate equals the number of bits transmitted per second, because each bit is carried by one symbol in the signal. Common UART baud rates include 9600, 19200, and 115200.

Even when the baud rate is set identically, the receiver only sees a bare data signal. If it samples this signal only once per bit period, severe errors can easily occur because there is no reference point. UART solves this with start-bit synchronization and oversampling: the receiver begins receiving data only after observing a start bit, and it samples the data signal at a multiple of the agreed baud rate. This multiple is typically a power of two, commonly 8, 16, or 32.

Taking 16× oversampling as an example, there are 16 sampling periods per data bit. The receiver’s sampling flow is as follows:

• Observe RX transitioning from high to low; begin sampling.
• After 8 sampling periods, check whether RX is still low. If so, treat this as the center of the start bit; if not, the previously observed transition was a noise glitch, and sampling stops.
• Sample RX every 16 sampling periods, using each as the center of a new data bit.
• Stop sampling after all data bits have been received.

Additionally, the two devices must agree on how many data bits are sent between the start and stop bits, and must stay consistent throughout the communication. We can also choose to append a parity bit after the data, indicating whether the transmitted data should contain an even or odd number of high bits, allowing the receiver to check for errors.

UART data transmission: 16× oversampling, 3 data bits, no parity bit.

Of course, just as two synchronized clocks will drift over time, the two devices’ individual baud rates may also have slight differences, causing error accumulation. In theory, however, the impact is small because:

• Before each data transmission, start-bit synchronization resets the timing, limiting error accumulation to within a single frame.
• By oversampling and choosing an appropriate sampling instant, we ensure that each sample is taken near the nominal center of the data bit; even a slight drift is unlikely to read the wrong level.

In practice, the UART protocol can tolerate a baud rate error of around 4% between the two devices.

Implementation

The UART protocol is generally implemented via dedicated hardware, requiring only calls to the corresponding low-level functions in code.

Beyond the provided low-level functions, many open-source UART libraries are available that greatly simplify debugging and development. For example, SerialAccessor is a serial debugging framework that enables a host computer to directly access MCU registers over UART. If time permits, I will also analyze the operating mechanism of this framework in detail, including topics such as DMA buffers.

Summary

We have covered the fundamental principles of the SPI, I2C, and UART serial communication protocols in detail. In practice, you can choose among them flexibly based on their characteristics and your actual requirements.

References

• Understanding the SPI Bus (SBOA621) - Texas Instruments
• Understanding the I2C Bus (SLVA704) - Texas Instruments
• Basics of I2C: Advanced Topics (TIPL6104) - Texas Instruments
• UART Protocol Overview - Texas Instruments
• IS31FL3731: Audio Modulated Matrix LED Driver - Lumissil Microsystems
• Description of STM32G4 HAL and low-layer drivers (UM2570) - ST Microelectronics

注意：本文是翻译版，仅供参考。英文原文在此。

双极结型晶体管 (BJT)

结构

想象一下，将一块 p 型材料夹在两块 n 型材料之间。当 p 型块较宽时，整个结构在功能上等效于两个阳极相连的独立 PN 结 (PN junction)。然而，当 p 型块变得非常窄时，两个 PN 结之间就会产生有趣的耦合 (coupling) 效应。

双极结型晶体管 (BJT) 正是采用了这种 “三明治” 结构，它由三块掺杂材料构成，每块材料各引出一个端子。我们先将 p 型材料置于中间，这种结构被称为 NPN BJT。

在平衡状态下，三个区域的费米能级 (Fermi level) 对齐，导致基区 (base region) 的电子能量出现一个 “凸起”。由于基区尺寸很小，该 “凸起” 的宽度很窄，因此从发射区 (emitter region) 扩散过来的电子有可能穿越基区而不与空穴复合，并被扫入集电区 (collector region)。

NPN BJT 的能级示意图。

工作区域

根据两个 PN 结（BE 结和 BC 结）上所加电压偏置的不同，BJT 工作于四种工作区域 (operating regions)，每种区域具有不同的特性：

正向放大区与反向放大区

首先考虑正向放大区，此时

• BE 结正向偏置 (\(v_{BE} > 0.7\,\mathrm{V}\))：大量电子注入基区；
• BC 结反向偏置 (\(v_C > v_B\))：存在宽耗尽区及强电场。

💡 实际应用中，BC 结轻微正向偏置也是可以容忍的，BJT 仍能工作在正向放大区，其阈值电压约为 \(v_{CE} \approx 0.3\,\mathrm{V}\)（即 \(v_{BC} \le 0.4\,\mathrm{V}\)）。

当注入（扩散）的电子进入基区时，由于基区宽度很窄，只有极少数电子会与那里的空穴复合。几乎所有注入的电子都会迅速遇到 BC 结耗尽区中的电场，并被立即扫入集电区。BC 结上的反向偏置进一步阻止了电子从集电极向基极的注入。因此，产生了很大的集电极电流 \(i_C\)。

空穴则需要由外部电流 \(i_B\) 向基区提供，但由于复合极少，基极电流很小。这样，BJT 有效地将基极电流放大为集电极电流，其增益 \(\beta\) 由下式给出：

通常取值范围在 \(50 \sim 200\) 之间。根据基尔霍夫电流定律，我们还有 \(i_E = i_B + i_C\)。

NPN BJT 正向放大区工作示意图。

💡 我们考虑电子的流动，因为它们是发射极和集电极端子的多数载流子 (majority carriers)。从基极向发射极注入空穴的现象也存在，但与电子注入相比可以忽略不计。

几乎所有注入的电子都被扫入集电区，因此我们可以近似认为 \(i_C \approx i_E\)。根据 PN 结的 I-V 特性方程，我们可以将 \(i_C\) 表示为与 \(v_{BE}\) 的指数关系，

其中

• \(I_S\) 是 BE 结的反向饱和电流，
• \(V_T := k_B T / q\)。在室温下，\(V_T \approx 26\,\mathrm{mV}\)。

💡 当 BJT 工作在正向放大区时，\(v_{BE}\) 很大，因此我们省略了 \(-I_S\) 项。

当我们改变集电区电压 \(v_{CE}\) 时，会发生更有趣的现象。\(v_{CE}\) 越高，BC 结反向偏置就越深，其耗尽区也越宽。更宽的耗尽区导致有效基区宽度减小，因此在基区复合的电子更少，导致 \(i_C\) 增大。这种效应称为厄利效应 (Early effect)。

考虑到厄利效应，我们可以写出关于 \(i_C\) 的完整方程：

其中 \(V_A\) 是厄利电压 (Early voltage)，典型值在 \(50 \sim 100\,\mathrm{V}\) 范围内。

BJT 的厄利效应示意图。

在反向放大区，偏置情况正好相反，因此 BJT 的工作方式也反过来：集电极向基区注入电子，这些电子被扫入发射区。

然而，集电极是中等掺杂，而发射极是重掺杂，这导致电子注入效率降低，并且电子被扫入发射区的难度增加，最终导致电流增益较小。这种工作方式性能不佳，因此反向放大区几乎没有实际应用。

饱和区与截止区

首先考虑饱和区，此时 BE 结和 BC 结均为正向偏置。

现在，当从发射极注入的电子进入基区时，由于 BC 结正偏，耗尽区变窄，因此被扫入集电区的电子减少。相应地，更多的电子将在基区与空穴复合，因此需要提供更大的空穴供应（即更大的基极电流）。此外，由于 BC 结也处于正偏，集电极将开始向基区反向注入电子。

因此，在饱和区中，

• \(i_B\) 增大，\(i_C\) 减小，导致增益 \(\beta\) 下降，
• 并且由于正向偏置电压 \(v_{CE}\) 很小且几乎恒定。

在饱和区，NPN BJT 的行为类似于一个闭合的开关，允许电流从集电极流向发射极。

NPN BJT 饱和区工作示意图。

在截止区，两个结均处于反向偏置，因此没有显著的载流子注入。NPN BJT 的行为类似于一个断开的开关，阻断电流流动。

PNP BJT 概览

我们也可以将 n 型材料放在中间，p 型材料放在两侧。这种结构称为 PNP BJT。在 PNP BJT 中，大多数原理与 NPN BJT 相似，但

• 多数载流子是空穴而非电子，
• 且所有极性（电流方向、特定工作区的结电压）均反转。

然而，空穴（位于价带）的迁移率低于电子（位于导带），因此在相同条件下，PNP BJT 的电流增益小于 NPN BJT。这也是 PNP BJT 使用较少的原因。

PNP BJT 示意图。

电路中的 BJT

NPN 和 PNP BJT 的电路符号。基极与发射极之间的箭头代表了 BE 结的极性方向。

现在，让我们将 BJT 连接到电路中并观察其效果。控制方程为

在接下来的讨论中，我们将使用 NPN BJT 进行演示。

电压传输特性

在实际应用中，BJT 通常连接成共发射极 (common-emitter) 组态，其中

• 发射极节点接地，
• 集电极节点作为输出电压，通过一个上拉电阻 \(R_C\) 连接到恒定电压源 \(V_{CC}\)，
• 基极节点作为输入电压。

当我们增加输入电压 \(v_{B}\) 时，输出电压 \(v_{C}\) 的曲线会呈现出不同的变化，对应三个不同的工作区域。

• 截止区：NPN BJT 几乎不导通，因此 \(v_{C}\) 可被视为 \(V_{CC}\)。
• 正向放大区：\(i_{C}\) 随 \(v_{B}\) 呈指数增长，因此由于上拉电阻上的压降增加，\(v_{C}\) 下降。
• 饱和区：当 \(v_{C}\) 降至 \(0.3\,\mathrm{V}\) 以下时，NPN BJT 进入饱和，\(v_{C}\) 近乎恒定。

共发射极组态及其电压传输特性。

我们可以看到，NPN BJT 在输入为高时输出为低，输入为低时输出为高，起到了 “反相” 数字开关的作用。另一方面，PNP BJT 在输入为高时输出为高，输入为低时输出为低，起到了 “同相” 数字开关的作用。这一特性使它们在数字电路中得以应用。但在实际生活中，由于以下原因，它们现在已很少用于数字电路：

• 功耗大：即使在不切换状态时，也存在持续的集电极电流。
• 扇出能力有限：源于虽小但不可忽略的基极电流。

它们在数字电路中的角色已大多被 MOSFET 所取代。

小信号分析

BJT 在模拟电路中常用作共发射极放大器 (CE amplifier)，其连接方式与上图类似。分析时，本节开头列出的三个方程是足够的。然而，它们都是非线性的，如果外部电路也很复杂，计算将是一场灾难。因此，为了便于计算，必须使用简化模型。

但是，为了简化方程，需要做出一些假设。

大信号与小信号

当信号的变化幅度很大时，无法恰当地进行任何近似。在这种情况下，我们必须使用完整的非线性方程。这种信号被称为大信号 (large signal)。

然而，当信号的变化幅度很小时，我们可以在信号所在的工作点附近进行线性近似。该工作点称为静态工作点 (quiescent point，简称 Q 点)，而信号本身称为小信号 (small signal)。

进行小信号分析时，一种常见的方法是将信号拆分为一个直流偏置和一个小的交流分量，分别进行分析，然后利用电路的叠加原理 (superposition principle) 合并它们的效果。

• 直流偏置决定了 Q 点，并确保 BJT 工作在正向放大区，
• 交流分量则被电路放大，其增益等于传输函数在 Q 点的斜率。

在本文中，我们使用大写字母 \(V_C\) 表示直流偏置，小写字母 \(v_c\) 表示交流分量。完整信号则用带大写下标的小写符号表示，如 \(v_{CE}\)。

💡 叠加原理要求电路是线性的，而 BJT 本身并非如此。然而，我们是在 Q 点处近似得到的线性电路模型上应用它，所以不必担心。

混合 π 模型 (Hybrid-\(\pi\) Model)

混合 π 模型本质上是 NPN BJT 在正向放大区 给定 Q 点处的一阶近似。它由三个电路元件构成：

• 集电极处的电压控制电流源 (跨导 \(g_m\))，
• 发射极与基极之间的电阻 \(r_\pi\)，
• 以及与电流源并联的电阻 \(r_o\)。

这些参数并非凭空出现的数字：它们捕捉了 BJT 的一阶特征效应。

混合 π 模型的电路图。

模型应用步骤

要应用混合 π 模型，需遵循以下步骤：

1. 根据直流偏置确定集电极电流 \(I_C\)（确定 Q 点）；
2. 计算模型中的参数；
3. 分别分析直流偏置和交流分量，然后利用叠加原理合并结果。

CE 放大器

核心结构

CE 放大器本质上是一个采用共发射极组态连接的 NPN BJT。它

• 工作于由 \(v_B\) 的直流分量决定的 Q 点，
• 将 \(v_B\) 的交流分量放大到 \(v_C\) 上。

通过混合 π 模型，我们可以推导出小信号电压增益为

由于源自厄利效应的输出电阻很大，通常增益可以进一步近似为 \(A_v \approx -g_m R_C\) 而不会有太大偏差。

然而，这种基本结构并非最优，原因包括：

• 直流分量的不可靠性：我们无法保证输入电压的直流分量足够稳定；
• 增益的敏感性：基极电压（影响 \(v_{BE}\)）或温度（影响 \(V_T\)）的微小波动，都会导致 \(i_C\) 的大幅变化，进而影响增益。

这些因素即使是对于很小的交流分量，也会引起显著的非线性效应。因此需要进行优化，我们可以从三个角度来解决这个问题。

优化措施

输入优化：交流耦合 (AC Coupling)

我们不能依赖输入电压的直流分量，这让我们的工作有些困难。但注意，我们手头有一个稳定的直流电压源 \(V_{CC}\)。因此，我们可以通过两个电阻对 \(V_{CC}\) 进行分压，并以此作为 BJT 的直流偏置。然后，只需将输入信号的交流分量通过电容耦合到这个直流偏置上即可。

我们该怎么做呢？想想电容器：它们隔断直流，允许交流通过。因此，我们可以取一个电容，一端连接到输入信号，另一端馈送到 \(v_{B}\)。根据叠加原理，\(v_B\) 现在将接收到来自 \(V_{CC}\) 分压的稳定直流分量，以及来自输入信号的交流分量。搞定！

输入交流耦合示意图。

💡 注意：在分析交流分量时，上拉电阻应视为接地，因为在进行交流分析时，恒定电压源 \(V_{CC}\) 是关断的。

BJT 优化：发射极退化 (Emitter Degeneration)

增益敏感性问题源于指数关系 \(i_C \propto \mathrm{e}^{v_{BE} / V_{T}}\)，这使得电压波动极难驾驭。运算放大器也类似：其开环增益也非常大且难以控制。然而，通过将输出反馈到运放的反相输入端，巨大的开环增益可以被驯服并用于负反馈调节。我们能否在这里也做些类似的事情呢？

当然可以！在裸露的 CE 放大器中，发射极直接接地，因此它无法动态适应基极电压的波动。因此，我们在发射极节点和地之间接入一个下拉电阻 \(R_E\)。让我们看看当集电极电流 \(I_C\) 略微增加时会发生什么。

• \(I_C\) 增加，导致
• 下拉电阻上的压降 \(I_CR_E\) 升高，进而导致
• 结电压 \(V_{BE}\) 下降，最终导致
• \(I_C\) 回落。

当 \(I_C\) 下降时，机理类似。因此，通过在发射极添加下拉电阻，我们可以实现对 \(I_C\) 的负反馈调节，从而获得更好的线性效果。这被称为发射极退化 (emitter degeneration)。

但这一优化是有代价的：电压增益会降低。电路分析显示，降低后的增益为（省略小项）

并且如果 \(g_m R_E\) 项足够大，增益将变为 \(A_v \approx -R_C / R_E\)，完全独立于 BJT 自身，从而消除了制造过程中 \(\beta\) 的误差带来的影响。

通过小信号分析可以推导出发射极退化前后的关键参数。

这种调节主要针对直流分量而非交流分量，但一个简单的下拉电阻会同时影响直流和交流。为了最小化这种权衡，我们可以在 \(R_E\) 上并联一个电容 \(C_E\)，允许交流分量将其旁路，以提高其增益。为了更精细的控制，我们甚至可以将 \(R_E\) 分成两部分，并仅在其中一部分上并联 \(C_E\)。

带有旁路电容 (bypass capacitor) 的发射极退化示意图。

负载优化：电容耦合

真正的晶体管很少独立工作。因此，需要将一个 CE 放大器的输出用于驱动负载或下一级 CE 放大器，而这通常只需要输出端的交流分量。所以，在实际输出之前，常在集电极端连接另一个耦合电容，以去除输出信号中的直流分量。

完整结构

通过以上三项优化，我们成功地将一个不稳定的 BJT 放大器升级为一个全面、稳健的 CE 放大器。它现在

• 通过将输入的交流分量耦合到由 \(V_{CC}\) 分压产生的直流偏置上，实现了稳定的性能，
• 通过发射极退化创造了外部可控的增益，
• 并通过输出端的电容耦合允许多级连接。

完整的 CE 放大器电路。

总结

在我们对 BJT 的探索中，我们看到了 BJT 的耦合效应所能产生的惊人特性，这比简单地将两个二极管背靠背连接要有趣得多。其接入电路后的小信号特性也同样引人入胜，使 BJT 成为现代模拟电路的基石，并在 CE 放大器等领域得到了广泛应用。

参考文献

• Ve311 课程 2026 年夏季学期课堂讲义，由 卢旭阳 教授讲授。

注：本文中的 BJT 全称为 Bipolar Junction Transistor，与商务日语考试（Business Japanese Test）无关，但祝考后者的人也顺利通过。🌟

Note: You may view the Chinese translation of the post here, but it is only for reference.

Bipolar Junction Transistors (BJT)

Structure

Imagine sandwiching a block of p-type material between two blocks of n-type materials. When the p-type block is wide, the whole structure is functionally equivalent to two independent PN junctions with their anodes connected. However, interesting coupling effects will occur between the two PN junctions when the p-type block becomes very narrow.

A bipolar junction transistor (BJT) takes the exact structure as this “sandwich”, consisting of three blocks of doped materials each acting as a terminal. Let’s put the p-type material in the middle first, which is known as an NPN BJT.

At equilibrium, the Fermi levels of the three regions match, resulting in a bump in the electron energy of the base region. Due to the size of the base region, the width of the “bump” is narrow, so there is a possibility of diffused electrons from the emitter region to cross the base region without recombining with holes and get swept into the collector region.

Visualization of the energy levels of a NPN BJT.

Operating Regions

Depending on the voltage biases on the two PN junctions (BE and BC), the BJT works in four operating regions, each with different characteristics:

Forward Active and Reverse Active

Consider forward active region first, where

• BE forward-biased (\(v_{BE} > 0.7\,\mathrm{V}\)): large amount of electrons injected into base region; and
• BC reverse-biased (\(v_C > v_B\)): large depletion zone with large electric field.

💡 In practice, a slight forward bias is also tolerated by the BC junction for the BJT to work in the forward active region, with the voltage \(v_{CE} \approx 0.3\,\mathrm{V}\) as the threshold (i.e. \(v_{BC} \le 0.4\,\mathrm{V}\)).

When the injected (diffused) electrons enter the base region, only few of them recombine with holes there due to the narrow width. Almost all injected electrons will quickly see the electric field in the BC junction’s depletion zone and be swept immediately into the collector region. The reverse bias on the BC junction further prevents electron injection fron the collector to the base. Therefore, a large collector current \(i_C\) is present.

Holes need to be supplied to the base region by an external current \(i_B\), but since recombination is rare, the base current is small. In such, the BJT effectively amplifies the base current as the collector current, with the gain \(\beta\) given by

and typically in the range of \(50 \sim 200\). We also have \(i_E = i_B + i_C\) due to Kirchhoff’s Current Law.

Visualization of the forward active region of a NPN BJT.

💡 We consider the flow of electrons because they are the majority carriers on the emitter and collector terminals. Injection of holes from base to emitter also exist, but remains insignificant as compared to the injection of electrons.

Almost all injected electrons are swept into the collector region, so we can approximate \(i_C \approx i_E\). By the PN junction’s I-V characteristic equation, we can describe \(i_C\) in terms of \(v_{BE}\) as an exponential,

where

• \(I_S\) is the reverse saturation current of the BE junction, and
• \(V_T := k_B T / q\). At room temperature, \(V_T \approx 26\,\mathrm{mV}\).

💡 When operating in the forward active region, \(v_{BE}\) is large, so we drop the \(-I_S\) term.

Something more interesting will happen as we change the voltage of the collector region \(v_{CE}\). The higher \(v_{CE}\) is, the more reverse-biased the BC junction becomes, and the wider its depletion region is. A wider depletion region causes a smaller base effective width, so even fewer electrons recombine in the base region, leading to a larger \(i_C\). This effect is called the Early effect.

Taking into account the Early effect, we can write the complete equation on \(i_C\) as

where \(V_A\) is the Early voltage, typically in the range of \(50 \sim 100\,\mathrm{V}\).

Visualization of the Early effect of a BJT.

In the reverse active region, the biases are the opposite, so the BJT works the other way around: the collector injects electrons into the base, which gets swept into the emitter region.

However, the collector is mildly doped and the emitter is heavily doped, which leads to weaker electron injection and increased difficulty of sweeping electrons into the emitter region, eventually causing smaller current gain. This is suboptimal, so the reverse active region has barely any application.

Saturation and Cutoff

Consider saturation region first, with the BE and BC junctions both forward-biased.

Now, as the injected electrons from the emitter enters the base region, the depletion zone becomes narrower due to the forward-biasing of the BC junction, so less electrons get swept into the collector region. In turn, more electrons will be recombined with holes in the base region, so the supply of holes must be larger. Moreover, since the BC junction is also in forward bias, the collector will start injecting electrons back to the base.

Therefore, in the saturation region,

• \(i_B\) increases, \(i_C\) decreases, leading to reduced gain \(\beta\), and
• the voltage \(v_{CE}\) is small and nearly constant due to forward-biasing.

In the saturation region, the NPN BJT behaves like a closed switch, conducting current from the collector to the emitter.

Visualization of the saturation region of a NPN BJT.

In the cutoff region, both junctions are in reverse bias, so there is no significant injection of carriers. The NPN BJT behaves like an open switch, blocking current flow.

PNP BJTs at a Glance

We can also put the n-type material in the middle, and the p-type material on the sides. This configuration is known as a PNP BJT. In a PNP BJT, most principles are similar to a NPN BJT, but

• the majority carrier are holes instead of electrons, and
• all polarities (current direction, junction voltage for a specific region) are reversed.

However, holes (in the valence band) have less mobility than electrons (in the conduction band), so the current gain of a PNP BJT is smaller than that of an NPN BJT under the same conditions. This is the reason why PNP BJTs are less commonly used.

Visualization of a PNP BJT.

BJTs in Circuits

Circuit diagram for NPN and PNP BJTs. The arrow between the base and emitter resembles the polarity of the BE junction.

Now let’s connect the BJTs into a circuit and observe the effects. The governing equations are

In the discussions below, we will be using NPN BJTs for demonstration.

Voltage Transfer Characteristics

In real-world applications, a BJT is usually connected in a common-emitter configuration, where

• the emitter node is grounded,
• the collector node, used as the output voltage, is connected to a constant voltage source \(V_{CC}\) by a pull-up resistor \(R_C\), and
• the base node is used as the input voltage.

As we increase the input voltage \(v_{B}\), the output voltage \(v_{C}\) curve will behave differently, corresponding to three different operating regions.

• Cutoff: The NPN BJT barely conducts, so \(v_{C}\) can be seen as \(V_{CC}\).
• Forward active: \(i_{C}\) increases exponentially with \(v_{B}\), so \(v_{C}\) decreases due to the increasing voltage drop on the pull-up resistor.
• Saturation: The NPN BJT saturates when \(v_{C}\) drops below \(0.3\,\mathrm{V}\), with \(v_{C}\) nearly constant.

Common-emitter configuration and its voltage transfer characteristics.

We can see that NPN BJT outputs low when input is high, and outputs high when input is low, functioning as an “inverted” digital switch. On the other hand, a PNP BJT outputs high when input is high, and outputs low when input is low, functioning as a “normal” digital switch. This property makes them applicable in digital circuits. But in real life, they are now rarely used due to their

• large power consumption even when not switching because of consistent collector current, and
• limited fanout arising from small but non-negligible base current.

Their roles in digital circuits are largely taken over by MOSFETs.

Small-Signal Analysis

BJTs are often used as common-emitter amplifiers (CE amplifiers) in analog circuits, connected similarly to the figure above. For analysis, the three equations listed at the beginning of this section are sufficient. However, they are nonlinear, and computation will be a disaster if the outer circuit is also complex. Therefore, simplification models are necessary for the ease of computation.

But, in order to simplify the equations, some assumptions need to be made.

Large Signal and Small Signal

When the variation of the signal is large, no approximation can be made appropriately. In this case, we have to use the full nonlinear equation. This signal is called large signal.

However, when the variation of the signal is small, we can make a linear approximation around the point where the signal lies. This point is called the quiescent point (Q-point for short), and the signal itself is called small signal.

When doing small signal analysis, one common method is to split the signal into a DC bias and a small AC component, analyze them separately, and combine the effects using the superposition principle of circuits.

• The DC bias determines the Q-point and ensures operation in the forward active region, while
• the AC component gets amplified by circuit, its gain equal to the slope of the transfer function.

In this post, we use uppercase \(V_C\) to refer to the DC bias, while lowercase \(v_c\) to describe the AC component. The full signal is represented as lowercase symbol with uppercase subscript, \(v_{CE}\).

💡 The superposition principle requires the circuit to be linear, which is not the case for the BJT. However, we are applying it on the linear circuit model approximated at the Q-point, so no worry.

The Hybrid-\(\pi\) Model

The hybrid-\(\pi\) model is essentially the first-order approximation of an NPN BJT in the forward active region given the Q-point. It consists of three circuit elements,

• a voltage-controlled current source (transconductance \(g_m\)) at the collector,
• a resistor \(r_\pi\) between the emitter and base, and
• a resistor \(r_o\) in parallel with the current source.

The parameters are not just magic numbers: they capture characteristic first-order effects of a BJT.

The hybrid-π model's circuit diagram.

Applying the Model

In order to apply the hybrid-\(\pi\) model, the following steps are taken:

1. Find the collector current \(I_C\) from the DC bias (determine the Q-point);
2. Compute the parameters in the model;
3. Analyze the DC bias and AC component separately, then combine using superposition principle.

The CE Amplifier

Core Structure

A CE amplifier is essentially an NPN BJT connected using the common-emitter configuration. It

• works at the Q-point determined by the DC component of \(v_B\), and
• amplifies the AC component of \(v_B\) into \(v_C\).

By the hybrid-\(\pi\) model, we can derive the voltage gain of the small signal as

Since the output resistance coming from the Early effect is large, typically the gain can be further rounded to \(A_v \approx -g_m R_C\) without being too far off.

However, this setup is not optimal due to several reasons, including

• Unreliableness of DC component: we cannot guarantee that the DC component of the input voltage is stable enough; and
• Sensitivity of gain: a small fluctuation in either base voltage (affecting \(v_{BE}\)) or temperature (affecting \(V_T\)) results in a large change in \(i_C\), thus affecting gain.

These factors will cause significant non-linear effects even for a small AC component. So optimizations are needed, and we can approach the problem from three perspectives.

Optimizations

Input Optimization: AC Coupling

We cannot rely on the DC component of the input voltage, which makes our life a bit hard. But look, we have a stable DC voltage source \(V_{CC}\) at hand. So let’s divide the voltage of \(V_{CC}\) by two resistors and use that as the DC bias for the BJT. Then, we can simply couple the AC component of the input signal onto that DC bias.

How can we do that? Think of capacitors: they block DC and allow AC passage. Therefore, we can take a capacitor, connect one end to the input signal, and feed the other end into \(v_{B}\). By the superposition principle, \(v_B\) will now receive a DC component from the division of \(V_{CC}\) which is stable, and an AC component from the input signal. Done!

Visualization of input AC coupling.

💡 Caution: when analyzing the AC component, the pull-up resistor should be tied to the ground, because the constant voltage source \(V_{CC}\) is turned off for AC analysis.

BJT Optimization: Emitter Degeneration

The problem with the sensitivity of the gain lies in the exponential relationship \(i_C \propto \mathrm{e}^{v_{BE} / V_{T}}\), making voltage fluctuations incredibly difficult to harness. An operational amplifier is similar: its open-loop gain is also very large and hard to control. However, by feeding the output back to the inverting terminal of an op-amp, the huge open-loop gain can be tampered and used in negative-feedback regulation. Can we do something similar here?

Absolutely! In a naked CE amplifier, the emitter is hard-wired to the ground, so it cannot adapt dynamically to the fluctuation in the base voltage. So in response, we connect a pull-down resistor \(R_E\) between the emitter node and the ground. Let’s see what happens when we increase the collector current \(I_C\) a little.

• \(I_C\) increases, causing
• the voltage drop \(I_CR_E\) on the pull-down resistor to rise, which results in
• a decrease of the junction voltage \(V_{BE}\), and finally leads to
• a drop in \(I_C\).

When \(I_C\) dips down, the mechanism is similar. Therefore, by adding a pull-down resistor on the emitter, we can achieve a negative-feedback regulation on \(I_C\), which leads to a better linear effect. This is called emitter degeneration.

But this optimization comes at a cost: the voltage gain will decrease. Circuit analysis reveals the reduced gain to be (small terms omitted)

and if the term \(g_m R_E\) is large enough, the gain becomes \(A_v \approx -R_C / R_E\), which is completely independent of the BJT itself, eliminating the impact of errors on \(\beta\) during manufacture.

Key parameters before and after emitter degeneration are derived from small signal analysis.

The regulation is targeted mainly at the DC component but not AC, but a simple pull-down resistor affects both DC and AC. To minimize this trade-off, we can connect a capacitor \(C_E\) in parallel with \(R_E\), allowing the AC component to bypass it in order to increase its gain. For more finer control, we can even divide \(R_E\) into two parts and connect \(C_E\) in parallel with only one of them.

Visualization of emitter degeneration with bypass capacitor.

Load Optimization: Capacitor Coupling

Real transistors rarely operate individually. As a result, there is a need for the output of one CE amplifier to drive a load or another CE amplifier at the next stage, which typically requires only the AC component at the output. Therefore, another coupling capacitor is often connected at the collector terminal before the actual output to remove the DC component of the output signal.

Complete Structure

With the above three optimizations, we have successfully upgraded an unstable BJT amplifier into a full-blown, robust CE amplifier. It now

• achieves stable performance by coupling the input’s AC component onto the DC bias generated by dividing \(V_{CC}\) voltage,
• creates externally-manageable gain by emitter degeneration, and
• allows for multi-level connection by capacitor coupling on the output terminal.

The complete CE amplifier circuit.

Summary

In our expedition into BJTs, we have seen what amazing characteristics the BJT’s coupling effects can produce, which is a lot more interesting than simply two diodes connected back-to-back. Its small-signal properties when connected into a circuit are also intriguing, making BJTs a cornerstone in modern analog circuits with wide application in CE amplifiers.

References

• Lecture slides from the Ve311 course in Summer 2026, taught by Prof. Xuyang Lu (卢旭阳).

Note: BJT stands for “Bipolar Junction Transistor” in this text, not “Business Japanese Test.” But anyway, if you’re indeed taking the exam, I wish you pass with flying colors. 🌟

注意：本帖为翻译版，仅供参考。英文原帖在此。

硅的量子观点

价带与导带

硅的原子序数为 14，电子构型为 \([\text{Ne}]3\text{s}^2 3\text{p}^2\)。在孤立的硅原子中，电子的波函数和能级是清晰量子化且分立的，因此没有值得特别关注的特殊效应。

然而，在原子间距离与原子大小相当的硅晶体中，不同硅原子的波函数会显著重叠。这将导致合并与重组，最终形成：

• 位于较低能量的价带 (valence band)，以及
• 位于较高能量的导带 (conduction band)。

一个能带 (band)是包含许多可能能级的能量区域。

在价带和导带之间，存在一个带隙 (bandgap)，其中不存在任何能级。带隙的大小由两个能带之间的能量差来衡量，通常记为 \(E_g\)。对于硅，室温下 \(E_g = 1.12\,e\mathrm{V}\)。

两个能带及带隙的可视化。（图片取自课堂讲义）

电子与空穴

在 \(0\,\text{K}\) 时，价带被完全填满，导带则完全空着。

随着温度逐渐升高，一些电子会被激发并进入导带，在价带中留下空穴。带负电的电子可以在导带中自由移动，带正电的空穴也可以在价带中自由“移动”，因此它们都可作为电流载体，称为本征载流子 (intrinsic carrier)，其浓度记为 \(n_i\)。

💡 实际上，在价带中真正移动的仍然是电子，它们占据空穴并在别处留下新的空穴。但这种描述难以定量分析，因此采用等效的空穴描述。

我们先考虑电子。为了量化电子在两个能带中的分布，需要两个重要特性：

• 量子态密度 (quantum state density) \(g_c(E)\) 和 \(g_v(E)\)，即在能量 \(E\) 处单位体积单位能量内可用的量子态数目；
• 分布函数 (distribution function) \(f(E)\)，即能量为 \(E\) 的某一特定量子态被电子占据的概率。

电子是遵循泡利不相容原理的费米子，因此它们由费米-狄拉克分布函数 (Fermi-Dirac distribution function) 描述：

其中：

• \(T\) 是绝对温度，
• \(k_B\) 是玻尔兹曼常数 \(8.62 \times 10^{-5}\,e\mathrm{V\cdot K^{-1}}\)，
• \(E_f\) 是费米能级 (Fermi level)，它是反映电子电势的能量参考基准。同时，它也是一种统计描述，衡量费米-狄拉克分布中 50% 占据率的点。并不一定存在一个恰好位于 \(E_f\) 的能级。

因此，导带中的电子浓度 \(n\) 由以下积分给出：

对于价带中的空穴浓度 \(p\)，我们需要使用 \(1 - f(E)\)，即某一特定量子态未被电子占据的概率：

对于本征（纯）硅，产生一个电子总伴随着产生一个空穴，因此有 \(n = p = n_i\)，这进一步表明费米能级位于带隙中间，记作本征费米能级 (intrinsic Fermi level) \(E_i\)。

另一方面，该积分得出一个重要且通用的关系式：

其中 \(B\) 是依赖于材料的常数。对于硅，\(B = 1.08 \times 10^{31}\,\mathrm{K^{-3}\cdot cm^{-6}}\)。方程 \(n_i^2 = np\) 描述了由成对调节的电子与空穴浓度平衡，而 \(BT^3\exp\) 项量化了在特定条件下总共能产生多少载流子。

💡 快速计算：在室温 \(300\,\text{K}\) 下，本征硅的 \(n_i \approx 10^{10}\,\mathrm{cm^{-3}}\)，与原子浓度相比很小。因此，纯硅是电的不良导体。

掺杂

掺杂的意义

由于纯硅导电性差，我们需要向系统中引入额外的载流子。有两类材料值得考虑：

• 电子施主 (electron donor) 原子，其价壳层多 1 个电子，例如磷；
• 电子受主 (electron acceptor) 原子，其价壳层少 1 个电子（相当于多 1 个空穴），例如硼。

当施主多于受主时，电子浓度 \(n\) 会增加并成为多数载流子 (majority carrier)，称为 n 型掺杂 (n-type doping)。反之，空穴浓度 \(p\) 会增加并成为多数载流子，称为 p 型掺杂 (p-type doping)。

实际掺杂计算

在实际掺杂中，引入的施主和受主数量很大，因此可以安全地假设：

• 完全电离，即额外载流子的浓度等于掺杂剂 (dopant) 的浓度；
• 多数载流子浓度与额外载流子浓度相等。

以一个简单的 n 型掺杂为例：如果掺杂剂浓度为 \(N_D\)（\(N_D \gg n_i\)），由掺杂剂引入的额外电子浓度为 \(N_D^+\)，最终电子（多数载流子）浓度为 \(n\)，那么我们可以安全地假设 \(N_D = N_D^+ = n\)。然后，少数载流子 (minority carrier) 浓度可以通过 \(np = n_i^2\) 导出。

💡 想象一下水的质子自递平衡。这里的近似类似于酸碱溶液计算中使用的近似。

能级变化

掺杂剂的引入会移动费米能级的位置。在 n 型掺杂中，导带中有更多电子，因此电子占据导带的概率变大，导致费米能级上升。在 p 型掺杂中则相反。

定量方程如下，其中 \(q = e\) 为载流子电荷量：

费米能级变化的可视化，左为 n 型，右为 p 型。（图片取自讲义）

PN 结

一块孤立的掺杂材料是枯燥的。当 p 型和 n 型两块掺杂材料紧密接触时，真正的乐趣才开始，这被称为PN 结 (PN junction)。

扩散与漂移

PN 结中有两个特征因素相互作用：

• 多数载流子的扩散 (diffusion)，以及
• 少数载流子的漂移 (drift)。

当 PN 结处于平衡状态（无外加电压）时，扩散和漂移相互平衡，没有净电流流动。

从动力学角度

p 型材料含有高浓度的空穴和低浓度的电子。而 n 型材料则含有高浓度的电子和低浓度的空穴。由于这种浓度差，只要两种材料紧密接触，多数载流子的扩散就会发生：

• 电子将从 n 侧进入 p 侧。进入后，它们会与大量空穴接触并结合，实现电荷中和。扩散走的电子留下的是电离的、固定的 n 型掺杂剂，带有净正电荷；
• 空穴将从 p 侧进入 n 侧。进入后，它们会与大量电子接触并结合，同样实现电荷中和。扩散走的空穴留下的是电离的、固定的 p 型掺杂剂，带有净负电荷。

净扩散电流是从 p 侧流向 n 侧的。这个扩散过程将在接触表面产生一个没有自由移动多数载流子的耗尽区 (depletion zone)，其中 n 侧带正电，p 侧带负电。于是，这种电荷分布会产生一个内部电场，方向从 n 侧指向 p 侧，阻止进一步扩散。

该电场进一步引发少数载流子的漂移。p 侧的电子向 n 侧漂移，而 n 侧的空穴向 p 侧漂移，形成从 n 侧流向 p 侧的漂移电流。此漂移电流受少数载流子浓度的限制，因此内部电场的变化不会显著改变它。

从动力学角度看扩散 (D) 与漂移 (S) 的可视化。（图片取自课堂讲义）

💡 多数载流子因浓度差而扩散 \(\implies\) 耗尽区 & 内部电场 \(\implies\) 少数载流子因电场而漂移 \(\implies\) 净电流为零。

从能量角度

一块材料的费米能级衡量其电子的电势。由于平衡状态下 PN 结中没有净电流，因此 p 侧和 n 侧的费米能级应当相等。

为了实现这一点，p 侧的能级会上升，而 n 侧的能级会下降，形成一个称为内建电势 (built-in potential)的势垒 (potential barrier)：

其中 \(N_A\) 和 \(N_D\) 分别是 p 侧和 n 侧的掺杂浓度。这个势垒将被正在扩散的多数载流子看到，从而阻挡其流动。

从能量角度看内建电势的可视化。（图片取自课堂讲义）

外加偏压

当 PN 结接入电路时，可以作为二极管 (diode)使用，将电流限制为仅单向流动。首先，我们来讨论 PN 结在外加电压 \(V_a\) 作用下的行为。有两种情况：

• p 侧电位更高，称为正向偏置 (forward bias)；
• n 侧电位更高，称为反向偏置 (reverse bias)。

正向偏置与反向偏置

当 PN 结的 p 侧电位更高（正向偏置）时，其费米能级因电压源拉走电子而下降。另一边，n 侧电位更低，接受电压源推入的电子，其费米能级上升。因此，势垒降低为 \(\phi_i - V_a\)，耗尽区变窄，进而导致扩散电流显著增加。最终结果是 PN 结中由扩散的多数载流子承载的较大正向电流。

当 PN 结的 n 侧电位更高（反向偏置）时，其费米能级上升；反之，p 侧的费米能级下降。于是，势垒增加到 \(\phi_i + V_a\)，耗尽区展宽，进一步阻挡扩散。最终结果是 PN 结中由漂移的少数载流子承载的很小的反向电流。

在电压偏置 \(V_a\) 下，PN 结中的电流为：

其中 \(I_S\) 是反向饱和电流，本质上是前面描述的漂移电流。

💡 可以观察到，当 \(V_a\) 为正时，由于指数关系，二极管电流 \(I_D\) 会急剧增加。因此，绝不应在无串联电阻的情况下将二极管置于正向偏置。

正向偏置（左）与反向偏置（右）的可视化。（图片取自讲义）

反向击穿

反向偏置不能无限增加。当反向偏置电压超过某个阈值 \(V_{BR}\) 时，PN 结的反向电流会急剧增大，这意味着它不再能限制电流单向流动。这种现象称为击穿 (breakdown)。

击穿有两种机制：雪崩击穿 (avalanche breakdown) 和齐纳击穿 (Zener breakdown)。

• 雪崩击穿：反向偏压极高，使得一个自由电子获得足够的能量，在碰撞时将另一个价电子“撞击”到导带，从而产生新的电子-空穴对。这些新载流子加速后与其他电子碰撞，又可产生更多电子-空穴对，最终引发链式反应，导致新产生载流子的“雪崩”，进而产生大电流。雪崩击穿通常难以控制，因此在大多数情况下是不可预期甚至不受欢迎的。
• 齐纳击穿：反向偏压导致电子“隧穿”通过带隙，直接从价带跃迁到导带，而无需跨越势垒所需的动能。这是一种量子力学效应，通常发生在耗尽区非常窄的重掺杂 PN 结中。与雪崩击穿不同，齐纳击穿具有几乎恒定的反向击穿电压，易于利用，因此被用来设计和制造稳压器 (voltage rectifier)。

PN 结的 I-V 特性，包括反向击穿。（图片取自课堂讲义）

总结

以上内容讲述了从硅的物理性质到 PN 结应用的完整故事。硅晶体提供了分离的价带和导带，掺杂提高了载流子浓度，而 PN 结利用了两种掺杂类型之间的扩散和漂移。PN 结可作为二极管使用，是当今所有电子电路的基石。

参考文献

• Ve311 课程 2026 年夏季学期课堂讲义，由 卢旭阳 教授讲授。

Note: You may view the Chinese translation of the post here, but it is only for reference.

Quantum View of Silicon

Valence and Conduction Bands

Silicon has an atomic number of 14, and its electron configuration is given by \([\text{Ne}]3\text{s}^2 3\text{p}^2\). In an isolated silicon atom, the electrons’ wavefunctions and energy levels are cleanly quantized and discrete, so there are no special effects worth attention.

However, in a silicon crystal where the interatomic distance is comparable to the size of atoms, the wavefunctions of different silicon atoms overlap significantly. This will lead to merging and recombination, and the net result is

• a valence band at the lower energies, and
• a conduction band at the higher energies.

A band is an energy region containing many possible energy levels.

Between the valence band and the conduction band, there is a bandgap, in which there are no energy levels existing. The size of the bandgap is measured by the energy difference between the two bands, typically denoted as \(E_g\). For silicon, \(E_g = 1.12\,e\mathrm{V}\) at room temperature.

Visualization of two bands and bandgap. (Picture taken from lecture slides)

Electrons and Holes

At \(0\,\text{K}\), the valence band is completely filled, and the conduction band is completely empty.

As temperature gradually increases, some electrons will be excited and enter the conduction band, leaving behind holes in the valence band. The negatively charged electrons can move freely in the conduction band, and the positively charged holes can also “move” freely in the valence band, so they both act as current carriers, called intrinsic carriers, whose concentration is denoted as \(n_i\).

💡 Actually, in the valence band, it is still the electrons that are actually moving, occupying holes and leaving behind new ones. However, that is difficult to describe quantitatively. Therefore, the equivalent description using holes is used.

Let’s consider electrons first. To quantify the distribution of electrons in the two bands, we need two important characteristics,

• the quantum state density \(g_c(E)\) and \(g_v(E)\), which is the number of available quantum states per unit volume per unit energy at energy level \(E\), and
• the distribution function \(f(E)\), which is the probability that a specific quantum state with energy \(E\) is occupied by an electron.

Electrons are fermions that obey the Pauli Exclusion Principle, so they are described by the Fermi-Dirac distribution function as follows,

where:

• \(T\) is the absolute temperature,
• \(k_B\) is the Boltzmann constant \(8.62 \times 10^{-5}\,e\mathrm{V\cdot K^{-1}}\), and
• \(E_f\) is the Fermi level, which is an energy reference that reflects the electric potential of electrons. It is also a statistical description, measuring the 50% point of the Fermi-Dirac distribution. There does not necessarily exist an energy level that is exactly at \(E_f\).

The electron concentration \(n\) in the conduction band is thus given by the integration

For the hole concentration \(p\) in the valence band, we need to use \(1 - f(E)\) which is the probability that a specific quantum state is NOT occupied by an electron,

For intrinsic (pure) silicon, the generation of an electron always comes with the generation of a hole, so we have \(n = p = n_i\), which further implies that the Fermi level sits in the middle of the bandgap, denoted as the intrinsic Fermi level \(E_i\).

The integration, on the other hand, yields an important, general relation,

where \(B\) is a material-dependent constant. For silicon, \(B = 1.08 \times 10^{31}\,\mathrm{K^{-3}\cdot cm^{-6}}\). The equation \(n_i^2 = np\) describes a balance in electron and hole concentrations adjusted by pairing, while the \(BT^3\exp\) term quantifies how much carriers in total can be generated under the specific conditions.

💡 Quick calculation: At room temperature \(300\,\text{K}\), \(n_i \approx 10^{10}\,\mathrm{cm^{-3}}\) for intrinsic silicon, which is small compared to the atom concentration. Therefore, pure silicon is a poor conductor.

Doping

Meaning of Doping

Since pure silicon conducts poorly, we need to introduce additional carriers into the system. There are two types of materials worth considering, including

• electron donor atoms that has 1 electron more in the valence shell, such as phosphorus, and
• electron acceptor atoms that has 1 electron less (equivalent to 1 hole more) in the valence shell, such as boron.

When donors are more than acceptors, the electron concentration \(n\) will increase and become the majority carrier, so it is called n-type doping. Otherwise, the hole concentration \(p\) will increase and become the majority carrier, called p-type doping.

Realistic Doping Calculation

In realistic doping, the introduced donors and acceptors are large in quantity, so it is safe to assume

• full ionization, meaning that the concentration of additional carriers is equal to the concentration of the dopant, and
• the concentrations of majority carriers and additional carriers are equal.

Take a simple n-type doping as example: if the dopant concentration is \(N_D\) (\(N_D \gg n_i\)), the concentration of additional electrons by the introduction of the dopant is \(N_D^+\), and the final concentration of electrons (majority carrier) is \(n\), then we can safely assume \(N_D = N_D^+ = n\). Then the minority carrier concentration can be derived from \(np = n_i^2\).

💡 Think of the autoprotolysis equilibrium of water. The approximations here are similar to those used in the calculations involving acid and base solutions.

Energy Level Changes

The introduction of dopants will shift the position of the Fermi level. In n-type doping, there are more electrons in the conduction band, so the probability of electron occupation in the conduction band will become larger, leading to a increase in the Fermi level. In p-type doping, vice versa.

The quantitative equations are, with \(q = e\) being the carrier charge,

Visualization of Fermi level change, n-type left, p-type right. (Picture taken from lecture slides)

The PN Junction

An isolated block of doped material is boring. The real fun begins when two blocks of p-type and n-type doped materials come into intimate contact, known as a PN junction.

Diffusion and Drift

Two characteristic factors interact in a PN junction:

• diffusion of majority carriers, and
• drift of minority carriers.

When the PN junction is in equilibrium (no external voltage applied), diffusion and drift balance each other, causing no net flow of current.

From the Dynamics Perspective

The p-type material contains high concentration of holes but low concentration of electrons. The n-type material, on the other hand, contains high concentration of electrons but low concentration of holes. Given this concentration difference, diffusion of majority carriers will occur as long as the materials are in intimate contact:

• Electrons will enter the p-side from the n-side. On their entrance, they will come in contact with an excess of holes and pair with them, charges neutralizing. Left behind by the diffused electrons are ionized, fixed n-type dopants with a net positive charge;
• Holes will enter the n-side from the p-side. On their entrance, they will come in contact with an excess of electrons and pair with them, charges also neutralizing. Left behind by the diffused holes are ionized, fixed p-type dopants with a net negative charge.

The net diffusion current is from the p-side to the n-side. This diffusion process will produce a depletion zone with no freely-moving majority carriers at the surface of contact, with positive charge in the n-side and negative charge in the p-side. The charge distribution will thus create an internal electric field, pointing from the n-side to the p-side, blocking further diffusion.

The electric field further induces drift of minority carriers. P-side electrons drift towards the n-side, while n-side holes drift towards the p-side, resulting in a drift current from the n-side to the p-side. This drift current is limited by the concentration of minority charges, so changes in the internal electric field will not alter it significantly.

Visualization of diffusion (D) and drift (S) from the dynamics perspective. (Picture taken from lecture slides)

💡 Majority carriers diffuse due to concentration difference \(\implies\) Depletion zone & internal electric field \(\implies\) Minority carriers drift due to electric field \(\implies\) zero net current.

From the Energy Perspective

The Fermi level of a block of material measures the electric potential of its electrons. Since there is no net current in the PN junction at equilibrium, the Fermi level of the p-side and n-side should match.

In order to achieve this aim, the energy levels of the p-side increase, while the energy levels of the n-side decrease, resulting in an potential barrier referred to as the built-in potential,

where \(N_A\) and \(N_D\) are the concentration of dopants on the p-side and n-side respectively. This potential barrier will be seen by the diffusing majority carriers, thus blocking its flow.

Visualization of the built-in potential from the energy perspective. (Picture taken from lecture slides)

Applying External Voltage

A PN junction can serve as a diode when connected into a circuit, regulating current to flow in only one direction. To begin with, we shall discuss how the PN junction behaves when an external voltage \(V_a\) is applied to it. There are two ways:

• p-side seeing higher potential, referred to as forward bias, and
• n-side seeing higher potential, referred to as reverse bias.

Forward Bias and Reverse Bias

When the p-side of the PN junction sees higher potential (forward bias), its Fermi level drops due to electrons being drawn away by the voltage source. On the other hand, the n-side sees lower potential, accepts electrons shoved into it by the voltage source, and its Fermi level rises. Therefore, the potential barrier is reduced to \(\phi_i - V_a\) and the depletion zone narrows, which in turn lead to a significant increase in diffusion current. The net result is a large forward current carried by the diffusing majority carriers in the PN junction.

When the n-side of the PN junction sees higher potential (reverse bias), its Fermi level rises, and conversely, the Fermi level of the p-side drops. The potential barrier is hence increased to \(\phi_i + V_a\) with depletion zone widening, which blocks diffusion even further. The net result is a small reverse current carried by the drifting minority carriers in the PN junction.

The current in the PN junction given a voltage bias \(V_a\) is

where \(I_S\) is the reverse saturation current, which is essentially the drift current described earlier.

💡 It can be observed that when \(V_a\) is positive the diode current \(I_D\) increases dramatically due to the exponential. Therefore, putting a diode in forward bias without a resistor in series should always be avoided.

Visualization of forward (left) and reverse (right) bias. (Picture taken from lecture slides)

Reverse Breakdown

Reverse bias cannot increase limitlessly. When the reverse bias voltage exceeds a certain threshold \(V_{BR}\), the PN junction will see an enormous increase in reverse current, meaning that it ceases to restrict current to flow in only one direction. This phenomenon is called breakdown.

There are two mechanisms of breakdown, avalanche breakdown and Zener breakdown.

• Avalanche breakdown: The reverse bias voltage is so high that a free electron gains enough energy to “knock” another valence electron into the conducting band on collision, thus creating a new electron-hole pair, which can further create more electron-hole pairs after acceleration and collision with other electrons, finally resulting in a chain reaction and causing an “avalanche” of newly-created charge carriers that produces a large current. Avalanche breakdown is typically hard to control, so it is not expected and even unfavorable in most scenarios.
• Zener breakdown: The reverse bias causes electrons to “tunnel through” the bandgap, directly jumping from the valence band to the conduction band without requiring the kinetic energy needed to cross the potential barrier. This is a quantum-mechanical effect, and typically happens to heavily-doped PN junctions with a very narrow depletion zone. Unlike avalanche breakdown, Zener breakdown has a nearly constant reverse breakdown voltage, making it easy to harness, so it is utilized to design and manufacture voltage regulators.

I-V characteristics of a PN junction, including reverse breakdown. (Picture taken from lecture slides)

Summary

Presented above is a complete story from the physical properties of silicon to the usage of PN junctions. Silicon crystals provide separate valence and conduction bands, doping increases carrier concentration, and PN junction makes use of diffusion and drift between two types of doping. PN junctions can serve as diodes, and they are the backbone of all electronic circuits used today.

References

• Lecture slides from the Ve311 course in Summer 2026, taught by Prof. Xuyang Lu (卢旭阳).